1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a self-aligned storage node.
2. Description of the Related Art
Because the function of a microprocessor becomes more powerful and its software program becomes more complicated, there is a correspondingly greater need for a high-capacity DRAM. As the integration of the DRAM increases, a memory cell, which comprises a transfer field effect transistor (TFET) and a storage capacitor, is commonly used.
As the DRAM integration increases, the size of a DRAM capacitor must be decreased. In order to maintain the capacity of the capacitor, the surface area of the capacitor must be increased. Thus, a stacked capacitor has been developed.
According to the fabrication process, the stacked capacitors are separated into two types: capacitor over bit line (COB) and capacitor under bit line (CUB). As the DRAM integration increases, an overlay margin between the storage node contact of the COB and the bit line is reduced. In order to provide sufficient space for forming the storage node contact, the width between the storage node contact and the bit line must be decreased as much as possible. This, in turn, causes difficulties in fabricating bit lines and may also break the bit lines.